Currently the peripheral units in a system, activate their interrupt lines whenever they need attention from the processor without any concern for what the processor may be doing. In a low power system, the processor may be in either an active state or a low power sleep state. It usually takes a finite number of cycles for a processor to transition into the low power sleep state from the active state, and similarly a finite number of cycles to transition from the low power sleep state to the active state.
When a peripheral activates its interrupt line, the processor transitions from the low power sleep state into an active state, if it was sleeping, to respond to the interrupt. As an example, there can be two peripherals A and B, each with a separate interrupt line. When the processor is in the sleep state, if peripheral A needs attention, the voltage on its interrupt line is changed. The processor will then come out of the sleep state into the active state to handle interrupt A and after it is done, the processor goes back to sleep. A short while later peripheral B activates its interrupt line and the processor repeats the wake-up sequence to handle interrupt B. This is wasteful in terms of power consumed and system resources used.
In general many peripherals have some amount of buffering which they can use to implement a certain level of slack with respect to when they need to interrupt the processor. For example, a serial interface may have a sixteen byte first in first out (fifo) memory to hold incoming characters. The serial interface may be configured to interrupt the processor as soon as one character has come in, or may be configured to interrupt the processor when the fifo memory is half full. Other options may be possible as well. For example an interrupt can be activated after one character is received if no character is subsequently received for two character times.
Similarly, disk requests from a processor typically go into a queue. The processor sets up several disk writes and reads and triggers the disk controller. The disk controller processes elements from the queue and can interrupt the processor at different times, after each successful operation, when the queue is half empty or when the queue is fully empty.
Yet another example relates to networking. Similar to disk operations, network transfers can also be queued. The network interface has the option of interrupting the processor at different thresholds.
In some cases the changing of thresholds may affect the correctness or smooth operation of the system. For instance if the serial interface delays the delivery of incoming bytes to the processor, the processor may not acknowledge receipt of the bytes and thereby prevent the transfer of subsequent bytes on the same serial line. However in many other cases, it is acceptable to modify the thresholds where the peripherals need to signal the processor. The setting of these thresholds is often driven by optimizing some metric such as user response time or total throughput depending on whether the machine is to be used as an interactive workstation or a server.